Robust Low-Leakage Circuits

Problem: While the aggressive scaling of CMOS technology to ever smaller dimensions has enabled higher performance and integration levels, it has given rise to a plethora of new problems in the design of integrated circuits [1-4]. Reduced threshold voltages and gate oxide thicknesses have caused an alarming increase in subthreshold source-drain leakage and gate leakage power dissipation in both active and standby modes of operation. As a result, leakage power has become an increasingly important fraction of the total chip power in the current technology generation. In addition, the wavelength of light used in current lithography systems is comparable to the minimum line dimension to be printed. This subwavelength lithographic regime has introduced several new sources of variation that has made the control of process variation more difficult [4-7]. Improved and novel VLSI methods will be essential in both highend processors and low-power designs to keep power dissipation manageable and maintain adequate process yields.